1. Field of the Invention
The present invention relates to electric circuit, and more particularly to an amplifier with noise separation.
2. Description of the Prior Art
In applications involving analog-to-digital converter (ADC), the processing of noise signal is a concern. For example, in an ADC or a digital-to-analog converter (DAC), increasing the signal-to-noise ratio (SNR) is regarded as an design consideration. One of the factors influencing the SNR is the transistor flicker noise. Flicker noise is an unwanted energy level that is generated when many dangling bonds appear at the interface between an oxide layer and the silicon substrate in the gate terminal of the transistor. When a charge carrier moves on the interface, some carriers are randomly captured and then released on the energy level to allow the drain terminal current to generate flicker noise. Therefore, reducing the flicker noise in an operational amplifier is a design concern.
The conventional methods for reducing flicker noise are described in the following:
(1) Enlarging the Area of the Transistor:
The relationship is provided below in the following formula (Razavi, B, “Design of Analog CMOS Integrated Circuits”, pp. 215, McGraw Hill):
            V      n      2        _    =            K                        C          OX                ⁢        WL              ⁢                  1        f            .      
From the above-described formula, it can be induced from the inverse proportion of the WL that the component area must increase as (f) noise signal decreases. Moreover, an accompanying stray capacitance acts to increase the chip power load. Generally, 1/f noise from a PMOS transistor is less than that of a NMOS transistor.
(2) The Utilization of an Auto-Zero Mechanism:
In one of the prior methods, an operational amplifier stores its own low frequency noise signals when not processing an input signal. The operational amplifier then waits until the next time segment to subtract the flicker noise from the input signal. The disadvantage of this method is that an additional capacitor is required for storing the low frequency noise signal, thereby increasing the chip area.
(3) The Utilization of a Chopper:
With reference to FIG. 1 and FIG. 2. FIG. 1 is a circuit diagram illustrating a chopper applied to an integrated circuit 100 in a Sigma-delta Modulator according to a conventional method. FIG. 2 is a timing diagram of the integrated circuit 100 shown in FIG. 1. About more detailed description, please refer to Yang et al. “A 114-dB, 68-mW Chopper-stabilized Sreeo Multi-bit Audio ADC in 5.62 mm2”, JSSC, vol. 38, no. 12, December 2003 and U.S. Pat. No. 4,939,516.
A chopper is therefore applied to modulate the flicker noise of the operational amplifier 110 from a low band to a high band. Such a circuit comprises eight additional switch components (forming the modulators 120 and 130), and comprises clock signals to control the switch components. Additionally, the chopper switch is applied during the middle of the duty cycle of the control signal Phi1. After the chopper switch has been finished, the recovery time at the output end of the operational amplifier 110 is half of the duty cycle of the control signal Phi1.